The present invention relates to a capacitive voltage divider as is used, for example, in analog-to-digital or digital-to-analog conversion of signals.
In conventional technology, capacitive digital-to-analog converters, in particular in connection with a comparator and a successive-approximation register, for forming an analog-to-digital converter are known. Such converters are applied, for example, in image sensors and are therefore generally suitable for low and medium resolutions as well as for being implemented on small surface areas.
Since said converters are implementable on small surface areas, parasitic capacitances constitute a problem for them. Due to the spatial vicinity of the structures, charge-carrying portions are close to one another, so that parasitic capacitances result. Digital-to-analog converters having capacitive voltage dividers, so-called capacitance-2-capacitance networks wherein capacitive elements from a series connection of a capacitance and the double capacitance thereof (also referred to as C2C=capacity-two-capacity) are used may be of interest for conversion, in particular, since they necessitate considerably fewer capacitances than comparable binary weighted capacitor arrays. For example, a 10-bit converter in a binary capacitance alignment necessitates about 1024 capacitances, whereas a C2C converter may make do with about 30 capacitances.
It is known that the linearity of C2C converters is substantially influenced by the parasitic capacitances of the capacitor array. In conventional technology, concepts such as predistortion, for example, are known for compensating for the parasitic capacitances. However, these methods have the disadvantage that they are highly dependent on exact knowledge of the parasitic capacitances. Thus, they are highly dependent on the implementation and cause higher production costs.
Efficient detection of analog signals necessitates integrating several low-noise, highly accurate analog and digital components. In various applications, such as for wireless sensor networks, CMOS image sensors (CMOS=complementary metal oxide semiconductor), biomedical implants, etc., data conversion places high demands on the performance and conversion behavior of the AD converters (AD=analog-to-digital) or DA converters (DA=digital-to-analog) used.
SAR ADCs (SAR=successive-approximation register, ADC=analog-to-digital converter) implemented in submicrometer technology are known, in conventional technology, for implementing analog-to-digital converters since they make do with reduced expenditure in terms of analog circuit technology, which is difficult and complicated to implement under conditions of low supply voltage. Binary weighted capacitive arrays are often used, in conventional technology, in successive-approximation ADCs. However, for each additional binary position, i.e. for each additional bit, the number of capacitances necessitated increases. The number of capacitances necessitated may increase exponentially with the number of binary positions to be converted. The maximally possible resolution of the ADCs is typically limited to about 8 to 10 bits, which is due to the high capacitance ratios and the low ratios between the available surface areas and the individual capacitances to be realized.
To avoid these problems, a C2C DAC may be used that is implementable on a comparatively small surface area, necessitates little power, and enables fast conversion as compared to binary DACs. What is disadvantageous about those C2Cs are the parasitic capacitances that arise at the inner connecting nodes and negatively influence the linearity of said C2C DACs. Because of the arising non-linearities, the resolution of C2C DACs is typically limited to 4 to 6 bits.
In conventional technology, various techniques are known which aim at reducing the parasitic effects, such as pseudo C2C ladders, cf. L. Cong and W. C. Black, “A New Charge Redistribution D/A and A/D Converter Technique-Pseudo C2C Ladder”, in Proc. 43rd IEEE Midwest Symposium on Circuits and Systems, August 2000, or fixed shield, cf. S. P. Singh, A. Prabhakar and A. B. Bhattcharyya, “C-2C Ladder Based D/A converters for PCM Codecs”; in IEEE Journal of Solid State Circuits, p. 1197-1200, December 1987, which, however, have not provided a satisfactory solution up to now. It is therefore problematic to implement C2C DACs necessitating a resolution of more than 6 bits.
A parasitic capacitance associated with a C2C ladder technology is illustrated in FIG. 8. FIG. 8 shows a C2C ladder structure wherein a first capacitance 801 is initially connected against a reference potential U0. In parallel with the capacitance 801, the series connection has two further capacitances 802 and 803 located therein which are also connected against the reference potential U0. In parallel with the capacitance 803, in turn, a further capacitance 804 is connected in series with a capacitance 805 against the reference potential U0. In parallel with the capacitance 805, a capacitance 806 and a capacitance 807 are in turn connected in series against the reference potential U0. In parallel with the capacitance 807, a capacitance 808 is in turn connected in series with a capacitance 809 against the reference potential U0, a capacitance 810 being additionally connected in parallel with the capacitance 809 in FIG. 8. FIG. 8 shows a capacitive voltage divider wherein the capacitances referred to by reference numerals 802, 804, 806, and 808, respectively, result from a parallel connection of two capacitances C and consequently each have a capacitance of 2C. By contrast, the capacitances 801, 803, 805, 807, 809, and 810 are realized by the capacitance C in FIG. 8.
A capacitive voltage divider results. The voltage divider may be operated such that the analog voltage to be converted is applied against the reference potential U0 at the capacitance 809. This results in a corresponding charge being stored within the capacitors 808, 809 and 810. It shall then be assumed in the following that this charge is stored within the respective capacitors and that no backflow of the charge is possible. By successively applying voltages to the nodal points 811, 812, 813, 814, or, alternatively, by applying corresponding reference potentials U0, a bit combination may be determined wherein a specific voltage, such as 0V, U0 or a minimum voltage, for example, results at the capacitor 809. In other words, in an iterative method, for example 5V are applied to the points 811, 812, 813, and 814, respectively. Depending on which point this voltage is applied to, this results in the voltage being divided along the capacitive voltage divider. The further this point is located away from the capacitor 809, the smaller the fraction of this voltage will be that ensures a charge transfer within the capacitors 808 and/or 809 and 810. If the correct bit combination is present—this may be detected, for example, by means of the smallest possible residual voltage at the capacitor 809—then the respective bit combination will have been found. Alternatively, the nodal points 811, 812, 813, and 814 may also be coupled to a reference potential, for example, and the terminals referred to by U0 in FIG. 8 may be connected to the respective bit voltages.
FIG. 8 further shows parasitic capacitances having the value 2 Cp between the respective tapping points 811 to 814 and at the capacitors 809 and 810. In FIG. 8, the parasitic capacitances exist in relation to the substrate, which in the example contemplated also is to have the reference potential U0. As may be seen from FIG. 8, the parasitic capacitances distort the linearity of the capacitive voltage divider. For example, the parasitic capacitances may represent a capacitance toward a bottom plate, a contacting or the like, a negligible capacitance of the upper limit of the semiconductor being assumed in this case. In principle, however, the parasitic capacitances may arise due to different layout variants within a semiconductor. The C2C DAC thus loses its linearity during the conversion process, since part of the charge is distributed across the parasitic capacitances during the conversion.